The present invention relates to improvements of a multiprocessor system.
In the multiprocessor system, a plurality of processor modules are connected to a common bus. Each processor module contains a clock signal supply block, a bus arbitration block, a bus control block, an address output block, a data input/output block, an internal bus, and an operation processing block (CPU).
In the processor module, when a bus access request is issued from the operation processing block, the bus arbitration block artibitrates the use of the common bus between the processor-module and the other processor modules. If none of the other processor modules is accessing the common bus, the requesting processor module obtains the right of using the common bus. When a plurality of processor modules simultaneously attempt to access the common bus, they are priority ordered and the processor module with the highest priority obtains the first access, then the module with the next high priority obtains the next access, and so on. The bus arbitration block having assigned bus access, activates level busy signal BS announcing to other processor modules that access has been assigned. The bus arbitration block then enables the bus control block and the address output block. Subsequently, addresses and data may be transferred between the operation processing output block and the common bus.
The processor module can be constructed with CMOS and can have a standby mode. In the standby mode, the supply of a clock signal is stopped during its operation to reduce power consumption. The conventional multiprocessor system, however, cannot accommodate the standby mode. This is a disadvantage of the conventional multiprocessor system. Another disadvantage of the conventional system is that when one processor module stops its operation, due to a failure which can be self-diagnosed, none of other processor modules can use the common bus. Specifically, when one processor module stops its operation while it is accessing its access to the common bus, the remaining processor modules cannot use the bus until all of the processor modules are temporarily disconnected from the common bus. In other words, to allow the use of the common bus by the remaining processor module, the busy signals of all of the processor modules must be temporarily made inactive.
In the conventional multiprocessor system, if one processor module stops during its access to the common bus, the busy signal of this processor module remains active. Therefore, the remaining processor modules are prohibited from subsequent use of the common bus.
Thus, the conventional multiprocessor system will not permit an individual system design which has a 1 standby function and allows operation stop due to a failure which can be self-diagnosed.